Intel Axes Rialto Bridge GPU, delays Falcon Shores to 2025

Jeff McVeigh, vice president and general manager of Intel’s super computing group, announced today via a blog post that Intel is canceling its upcoming Rialto Bridge series of GPU Max for data centers and moving to a two-year cadence for releases. of GPUs for data centers. So the company’s next data center GPU offerings will come in the form of hybrid chips based on the Falcon Shores chiplet, but the blog notes they’ll be in production by 2025, a year after Intel’s previous projections. of 2024.

HPC-focused Falcon Shores XPUs are designed for supercomputing applications and combine CPU and GPU technology in a combined chipset, but now they will first arrive as a GPU-only architecture in 2025. They were supposed to arrive as a CPU architecture +GPU in 2024, which means Intel’s positioning against competing products AMD and Nvidia, due for release this year, will be severely affected: Intel will now be several years late for a key architectural inflection point for higher end chips (more on that later).

Intel’s Falcon Shores XPU is key to competing with Nvidia’s Grace Hopper superchips and AMD Instinct MI300 data center APU. Nvidia’s Grace and AMD’s MI300 will be released this year with CPU and GPU cores in the same package with HBM memory. These designs represent a new type of architecture that provides tremendous benefits for HPC workloads and will be difficult or impossible to combine with hardware based on existing designs.

Intel tells us that the delayed Falcon Shores will come with only GPU cores in 2025, but hasn’t indicated when it will integrate the CPU cores into the design. As such, Intel’s HPC-centric designs will lag its competitors by several years. Furthermore, Intel will be forced to compete with the HPC-centric designs of AMD and Nvidia with their Xeon CPUs and Ponte Vecchio GPUs for several years, a significant disadvantage.

Falcon Shores represents the continuation of Intel’s heterogeneous architecture design arc with the ultimate goal of delivering 5x the performance per watt, 5x the compute density on an x86 socket, and 5x the memory capacity and bandwidth of existing server chips. Intel’s High Performance Computing (HPC) CPU and GPU roadmap converges with Falcon Shores, indicating that these chips will serve both roles in the future.

This disaggregated chip design will eventually have separate tiles of x86 compute and GPU cores, but Intel can use those tiles to create any combination of the two additives, such as a full CPU model, full GPU model, or a mixed ratio of the two. two. Intel notes that these tiles will be made on an unspecified Angstrom-era process node, though Intel’s 20A seems to fit the bill for tiles it could make itself.

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James D. Brown
James D. Brown
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