Cadence Announces First GDDR7 Verification Solution –

GDDR7 memory up to 36 Gbps per pin

Early adopters can now start testing their next-generation GDDR7 products.

Cadence is ready to ship the first verification solutions for GDDR7 technology to companies interested in providing their customers with the most advanced solutions. The announcement of Cadence’s first VIP (IP Verification) solution comes even before JEDEC (Joint Electronic Device Engineering Council) has formalized the final specifications for this new memory standard.

GDDR memory is designed for graphics and video processing solutions and has seen many iterations in recent years. The most recent upgrade is GDDR6, which is now used by the AMD Radeon RX 6000 and 7000 GPUs. Meanwhile, NVIDIA and Micron have developed their own standard called GDDR6X, which is the backbone of all high-end RTX 30 and 40 graphics cards. .

Cadence has now confirmed that GDDR7 will use PAM3 signaling, rather than the NRZ (non-return to zero/PAM2) used by GDDR6 or PAM4 used by GDDR6X technology. The company claims that PAM3 should have better SNR (signal to noise ratio) than PAM4.

According to Anandtech, this means that GDDR7 modules will offer up to 36 Gbps per pin, significantly improving speed over the existing standard. Of course, such speeds should not be expected from first generation GPUs using this technology, but it gives an idea of ​​how far this technology can go.

New features added in GDDR7


DRAM uses a single WCK clock for command address and data latching, while generating a divided by 4 internal clock called CK4 that is used as a reference for latencies.

The read clock in GDDR7 can be set to four different modes from the mode register:

  • Always running – As the name suggests, it is always running and stops during sleep modes
  • Disable: stops working when set to this mode
  • Start with the RCK Start command – The read clock can be started by issuing the RCK Start command before reading the data. It can be stopped with the RCK STOP command. Host can start/stop as per requirement
  • Start With Read – The read clock starts running automatically when the DRAM receives any command that involves reading data. Also, here, it can be stopped using the RCK STOP command.

With the help of the last two modes, power usage can be optimized by enabling RCK only during the periods when it is needed.

driving command:
In GDDR6, only one command can be issued at a time. The GDDR7 commands are coded in such a way that the row and column commands use different bits of the CA bus. Therefore, two independent commands can be issued in parallel. For example, Bank X can be updated by issuing an Update by Bank command in CA[2:0]while bank Y can be read by issuing a read command on AC[4:3] at the same time.

PAM3 signaling:
GDDR7 uses PAM encoding in high-speed operation for data, CRC, ERR feedback, and the read clock. In PAM3 mode, 256 bits of data are encoded and transferred in 8 WCK clock cycles. Significantly improves data rate compared to NRZ and has better SNR and eye margins compared to PAM4.

The first graphics cards based on GDDR7 should not be expected this year. However, the 2-year cadence for consumer graphics architectures may suggest that such solutions could appear in 2024.

Source: cadence

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James D. Brown
James D. Brown
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